I wish I had been in the room when they decided to ship literally any ARM device ever made
@sir is there a certain design decision that is causing you so much distress?
@sir i'm not super familiar with what constraints either arch places on the boot process. i recently remember you complaining about mode switching, is that part of the problem?
@syntacticsugarglider no, that's x86, which is a nightmare that works, as opposed to ARM, which is just a nightmare
@sir yeah I'm somewhat familiar with the x86 boot process, and I know that's what you were talking about, but I was wondering if your issues with ARM are the same. apparently not... so, what exactly makes the ARM boot process a nightmare (that doesn't work? my ARM devices appear to work)
@syntacticsugarglider the main problem is that there is not an "ARM boot process". There are $n ARM boot processes, where $n is equal to the number of ARM devices in existence
@sir ooh okay yeah I was not aware of that
that's a bit horrifying
seems like a relatively (operative word) easy thing to standardize too
@sir just use your own FPGA CPU already.
@lanodan is RISC-V bad outside of the boot story and device enumeration?
@lanodan it's just modular iiuc, each arch can support a subset of the features
@lanodan I dunno, I guess. It seems to me that G is a reasonably sane baseline to target, and the other instructions can be enabled on a case-by-case basis.
@sir here's how the evil was born:
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