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RISC-V fucking when

· brutaldon · 3 · 9 · 10

And for fuck's sake you lazy ass SoC designers would you please write some goddamn specifications for booting and device enumeration before trying to ship a revolutionary new ISA with fucking u-Boot and device trees

@sir Or for that matter do something like adopt Open Firmware? I mean, it already exists, has a *very* decent track record over the years, I don't see a particular reason why it isn't more widespread beyond NIH/wanting to lock down systems for no good reason

@sir Designing a SoC is hard and expensive (including the tools, often proprietary for the lack of choice, and the hardware designers are way scarcer than web-developers for example). Making it produced is even harder. Not only because this is objectively expensive, but also there is quite a lot of monopolization, and every company tries to secure the status quo. So you can't even buy what you need without going through the hell of negotiations.

@sir RISC-V is great and all, but it's (intentionally) not a complete spec. It was designed so you could make some real innovative stuff.

To make RISC-V processors that can go toe to toe with x86 and ARM, there needs to be an additional spec that standardizes RISC-V for general purpose processors.

Maybe that will happen as someone starts making successful RISC-V processors, becoming the de-facto standard, maybe it'll be set by a standards body. Either way it still needs to be done.

@urusan @sir what about PowerPC? IBM just released their POWER10 architecture, but their POWER9 architecture isn't a slouch either.

@urusan @sir
It being commercially viable will be a thing. The fact that Nvidia is going to compete against Intel and AMD means that this platform will get some nice monies for PR and R&D.

@sacha @sir I'm not doubting the eventual viability of RISC-V, I'm just pointing out that the road to a standardized RISC-V competitor to x86 and ARM is still pretty long.

For instance, check out this news article:
tomshardware.com/news/sifive-r

SiFive appears to be the chip engineering wing of the RISC-V Foundation, with one of the founders being the chairman of the RISC-V Foundation.

It is good to see that they are serious about creating the standard extensions required.

@sacha @sir It should be noted that RVV isn't at version 1.0 yet, so these first processors will probably be obsolete in a few years, when they aren't following the 1.0 spec. Either that or 1.0 will be tied to their release, since these two groups are so closely related.

github.com/riscv/riscv-v-spec

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